IBM cmos10lpe LVS error Device unbound

[r44133]

I am trying to layout a simple inverter with a triple well nfet in IBM's cmos10lpe process. LVS will not complete due to an error device 'subc(Generic)' on schematic is unbound to any layout device...Is anyone familiar with this issue and how to solve it? Thanks!

 

[oermens]

you need to add substrate contact in the layout. add an instance of subc in layout and connect it to the source of nmos. in schematic, the top of subc is connected to source, the bottom is connected to bulk.

 

[r44133]

I tried as suggest, but without success. Please see layout/schematic. Thanks

 

[oermens]

Why do you have guard ring AND subc? connect nwell to source of PMOS, psub to source of nmos and remove subc. or do as i did in attached (but it is 8rf not 10lpe).

 

[r44133]

I applied the psub using the ibm_pdk-misc, however I still got the same error. Then I ran connectivity->update->components and nets and the subc was created. So I attached the subc and that did not work. I got rid of the psub guardring and only wired the subc and that failed.

 

[oermens]

what error are you getting? still subc mismatch?

enable nwell contact in the schematic view of the pmos (nothing will change in schematic) then update the layout view and the nwell contact will be added. the schematic and layout i posted pass drc and lvs without issue.

the default guardring is a double guardring - nwell and psub contacts. the psub contact will extract as subc so you can delete the one which is added by vxl. if you have further issues your should refer to the design rule documents or contact the fab.

if you are a mosis customer download the 8rf training guide and refer to the section on substrate contact methodology, it should be the same for 10lpe.

 

[r44133]

I am still getting an error message of device 'subc(Generic)' on schematic is unbound to any layout device.

I contacted frytech before I posted on edaboard, but I am very low on their list.

The pfet does not have the nwell contact option in the schematic view. However the nfettw device has the option to put in a triplewell, pwell, and T3 layer. I checked those options and updated the layout. The layout looks great(see attached), but I still get the above error. If I take the subc out of the schematic, it will complete lvs. But it will give several errors in the lvs debug window, i.e., device mismatch for nfet, GND nets, and rewire.???

 

[oermens]

oh i did not realize you are using triple well fets. i never used these devices but there should be a section in your documentation about them.

 

[r44133]

Thanks oermens for your help!

I needed to pull the subc out of the nwell and check subc->parameter-> lvs marker layer on/off.

Thanks again!