I2C/ SMBUS slave design

[abhinavpr]

Hi,

I urgently need a simple I2C/smbus slave to be connected to a memory. It would be of great help if somebody can provide a simplistic design in verilog or docs


regards
abhinav pr

 

[rca]

there are some ip on opencore.org

 

[abhinavpr]

Hi,

i am designing an I2C slave module . the spec says data on SDA can only change when SCL is low. can somebody tell me how to achieve that .

for write operation its easy as we can sample SDA at rising edge of SCL as the data is stable before SCL rising edge

but how do we write into SDA during the READ operation? as the data must be written into SDA before the arrival of SCL rising edge.