i2c Master verilog design

[sunidrak]

I am stuck in designing I2C master using verilog . Can anybody plz guide me how to implement START and STOP condition in I2C master using verilog . How to create that start and stop condition using verilog I am not getting plz its very much urgent

 

[dpaul]

You should be more detailed in your question/s. Something like what you have already implemented and what is your 'bone of contention' right now. Perhaps some code snippets and then pin pointing out the problem, etc... or questions about parts of the protocol which you fail to understand would be good!

 

[sunidrak]

Thank your reply.

I am designing I2c master for my design like this . I did most of the coding but I am not getting how to define the START and STOP condition :-(

SCL =high
SDA=High---to--Low

SCL=High
SDA=Low--to--High

how to code this in verilog ??

If you have refernce design plz send It will be helpful

 

[FvM]

It's really not a big thing to design an I2C master from the scratch, just based on the Philips/NXP specification.

Besides using this straightforward approach, there are many I2C Verilog designs available from the internet.

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how to code this in verilog ??

Possible first steps
- design a clock enable signal with suitable rate, e.g. 4x I2C speed
- design a finite state machine that controls the bus states. You can either handle everything in a single FSM or make a hierarchical FSM topology
- design a shift register and bit counter for the data frame