I2C design doubt about hold time for the SDA signal

[always@smart]

i2c internally provide hold time

Hi all,

Has anyone here done I2C design before? Then I got a query for you.

Please refer to The I2C Bus Specification(version 2.1, January 2000). Page 32, Note 2: A device must internally provide a hold time of at least 300ns for the SDA signal.........

My doubt is:

Does it mean that if i'm a slave module, when I send data to a master(read command), I need to hold the data for 300ns after the falling edge of SCL?

What about input from the master(write command), does the slave have to internally give delay to the SDA data for 300ns?

Hope someone can answer my question.

Thanks in advance

Regards,

always@smart

 

[always@smart]

at least 300ns for sda

Please tell me ..I need to know urgently.

Regards,

 

[Mallmannen]

Re: I2C design doubt.......

Cant you getholf of some routines for sending i2c commands

 

[Kuehnsen]

The device must be able to hold the sda line down for this minimal time to aknowledge to the master!

What is your task, maybe you can find some nice routines for i2c-handling or use a controller with i2c-if for programing.

 

[always@smart]

Re: I2C design doubt.......

Hi all,

I'm actually designing a chip which using I2C interface as a slave module, that's why i need to know if the data need to be held for 300ns before it send out either the ACK or EEprom data to master.

So, as what i know so far, whoever be a transmitter MUST hold the data for at least 300ns(internal delay) and whoever act as receiver can directly latch the data directly without any "internal" delay, am I right?

please reply ASAP if you know

Thank you in advance

always@smart

 

[strive2004]

i think that the sda need to be held for 300ns.

 

[Noman Yousaf]

a bit of time is needed between scl hi to lo or lo to hi . and that must be about 300-to 1000 ns(1 us).

 

[jourval]

Re: I2C design doubt.......

Slave must hold this line low at least 300ns only as acknowledge
that data also send, btw how you can "hold" data? it is serial
interface - you can hold only last bit of data string, not more!
I had a lot problem with one fast D2A "I2C compatible" that gave low level 200 ns only, so that processor with built-in "truly" I2C sometimes completely loose the data

 

[sihuijian]

Re: I2C design doubt.......

It is the slaver responsibility to hold data for 300ns or more for the master correctly received the data sended from slave,I think you may use the mcu I/O pins to simulate the I2C interface,if so you need to internally delay 300ns then transfer next bit of data.if you use i2c interface from mcu itself then you need not delay 300ns since the interface
circuit automatically insert delay for you.

 

[ntfreak]

Re: I2C design doubt.......

If you are going to implement a I2C slave device I would recommend using a device with a I2C peripheral, it can be done in software - but can be a pain.
Many micros feature a I2C peripheral these days.
A I2C master is easy to implement in software, unless it is a multi-master system.

Regards
NTFreak