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With SOT package i found this: https://www.ti.com/product/adc121c021
It is at 189 kSPS, I2C, but it's difficult to handle sot packages, i prefer DIP.
Please review the datasheet, the maximum sample rates of the ADC121C021 are list in the A.C. and Timing Characteristics Table, Conversion Rate, Page 8:
A sample rate of 189 kSPS requires a I2C clock frequency of 3.4 MHz.
The sample rates for 100 kHz and 400 kHz clock frequencies are 5.56 kSPS and 22.2 kSPS respectfully.
While you've not mentioned the required resolution, even at 8 bits, it's exceedingly difficult to cram 65 kilobytes per second down a synchronous serial bus with only a 400 kHz clock, even without considering any overhead.
You would have better luck searching for an ADC in a DIP package with an SPI or parallel interface for your sample rate requirements.
Maxim offers a few ADCs with an SPI and parallel interfaces which could fulfill your sample rate requirements.
Also, you might want to specify what will be controlling the ADC.
BigDog
The ADC will be controlled by PIC18F4553. I want 1 ADC minimum to 6 ADCs maximum running simultaneously. So you suggest me to build my system around SPI protocol? What's the maximum speed i can reach with my PIC in SPI?
In Master mode, the SPI clock rate (bit rate) is user-programmable to be one
of the following:
• Fosc/4 (or TCY)
• Fosc/16 (or 4 • TCY)
• Fosc/64 (or 16 • TCY)
• Timer2 output/2
This allows a maximum data rate (at 48 MHz Fosc) of 12.00 Mbps.
And a last thing, can i have hot-plug with SPI? E.g to disconnect an ADC and microcontroller catch it like ACK on I2C?
Therefore while the SPI protocol utilizes the same MSSP module of the PIC18F4550, the maximum data rate of SPI far exceeds that possible of the I2C protocol, 1MHz Maximum Clock Rate, on the same device