If we choose low noise VCXO, something like Driscoll's Crystal Oscillator Topology
http://uwsdr.berlios.de/A New LNXO Topology.pdf , for example, and PLL chip like ADF4002 with lowest noise floor and choose very narrow PLL loop bandwidth (100-200Hz at 10MHz PHD), we will obtain phase noise at 10kHz from carrier 50MHz , which is defined only by phase noise of VCXO and frequency instability, which is defined by OCXO. Look Attachment, pls
We use this topology with AD9510 to x9 10MHz OCXO and to fanout it into 4 different low jitter clocks 90MHz