sooraj sreedhar
Newbie level 4
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 //Encoder section of hamming 3 `timescale 100 ps/ 100ps `ifdef SYNTHESIS module encoder(parity, state ); `else module encoder_rtl(parity, state ); `endif parameter N = 4; parameter M = 3; input [N-1:0] state; output [M-1:0] parity; generate begin genvar i; for (i = 0; i <M; i = i + 1) begin : calc_parity assign parity[i] = calculate_parity(state,i); end end endgenerate function automatic calculate_parity (input [N-1:0] state,//states in the input FSM input [M-1:0] i//parity bit representation ); begin reg [0:56]parity_table[0:5] = '{ 57'b1_0101_0101_0101_0101_0101_0101_0101_0110_1010_1010_1010_1101_0101_1011,//0 57'b1_1001_1001_1001_1001_1001_1001_1001_1011_0011_0011_0011_0110_0110_1101,//1 57'b1_1110_0001_1110_0001_1110_0001_1110_0011_1100_0011_1100_0111_1000_1110,//2 57'b1_1111_1110_0000_0001_1111_1110_0000_0011_1111_1100_0000_0111_1111_0000,//3 57'b1_1111_1111_1111_1110_0000_0000_0000_0011_1111_1111_1111_1000_0000_0000,//4 57'b1_1111_1111_1111_1111_1111_1111_1111_1100_0000_0000_0000_0000_0000_0000};//5 reg [N-1:0] masked; reg [N-1:0] masked_temp; reg result; result=0; masked_temp = parity_table[i]; //$display("parity_table=%b,i=%d",parity_table[i],i); masked = state & masked_temp; //$display("masked=%b,state=%b,masked_temp=%b",masked,state,masked_temp); result = ^masked; //$display("results=%d",result); return result; end endfunction endmodule
Here i have written hamming code encoder. But its for 57 bit .. I want to generalize that one.. and i want to directly find parioty bit by modulo 2 addition of corresponding bit..pls help mee
Last edited by a moderator: