I realized the code in vhdl....but still problems...

Hello...I want the code,in Xilinx....I realized the code in VHDL,but I don't know to traduce in Verilog...

Here is the code....but I have a problem at the counter...After 10 counters appears the number smaller with 10 that the previous number....

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity counter is
port( enable1: in std_logic;
clk: in bit;
reset, reset1: in bit;
bcd_d: out std_logic_vector(7 downto 0));

end counter;

architecture arch of counter is
signal qint, qint1: std_logic_vector(3 downto 0);
signal full1: std_logic;
begin

CNT1 : process (enable1, clk, reset)

-- declarations

begin
if reset = '1' then
qint <= (others => '0');
elsif clk='1' and clk'event then
if enable1 = '1' then
if qint(0) = '1' and qint(3) = '1' then

full1 <= '1';

qint <= (others => '0');

else
qint <= qint + 1;
full1 <= '0';
end if;
end if;
end if;
bcd_d(3 downto 0) <= qint;
end process;

CNT2: process (full1, clk, reset1)
begin
if reset1 = '1' then
qint1 <= (others => '0');
elsif clk='1' and clk'event then
if full1 = '1' then
if qint1(0) = '1' and qint1(3) = '1' then
qint1 <= (others => '0');

else
qint1 <= qint1 + 1;

end if;
end if;
end if;
bcd_d(7 downto 4) <= qint1;
end process;
end arch;

Can you traduce this in Verilog and correct the mistake?
Thank you a lot!

if I understand you correctly you've made a pretty
common mistake:
you want to make an action when
if qint(0) = '1' and qint(3) = '1' then
but you register this condition in full1 FF
then rest of your logic 'sees' the condition one clock
cycle later;
either change the value of qint which sets full1 from
'9' to '8' or change full1 from flip-flop to combo logic;
look at the attached waveforms where full1 is active
in my example code [top] and your code [below]

the verilog code itself:

---

Thank you a lot! Ieeeiiii! It works!
Thank tou!