From what I can remember global clock buffer are dedicated to route signal over specialized track inside the FPGA in order to minimize the skew from every block inside the device, is a sort of low timing path connected to every FF clock input that is inside the logic block.
just take a look at the language template, there are lots of example available.CLOCK_DEDICATED_ROUTE means that path is dedicated for clock,the path with least skew and is suitable to route clock.