Because an LSFR is just a shift register & a handful of xor gates. The shift register is the same length as your CRC polynomial.
Google CRC + LSFR and there is a great deal of information available.
Hi RBB, I got another question: what is the most efficient algorithm (area-wise) for doing a 16 bit/16 bit signed division in FPGA?? Thanks for the help!
Depends on your CRC size & your data size. If your CRC size is 8 bits and data size is 8 bits then you need an 256x8 LUT. If you used the LSFR approach it would take 8 flops & a couple of xor gates.
Why do you want a table? The "normal" hardware implementation (shift register + xor's) is very small and does one iteration every clock cycle. Even if you get the table memory for free, I think it is a very bad idea.
A table can speed up a software implementation, but a hardware implementation will be smaller and faster without a table.
A table in indeed a software approach - try to avoid this when targetting hardware (CPLD, FPGA, ASIC, Struct ASIC...).
The algorithm will indeed take only a couple of cells from you logic.
If you aren't sure about it. Make a test case and implement both, synthesize, and see what the outcome is.
This is true for your other question as well (16 bit division).