Hi Sinjani.
This VHDL file links together four sub-components:
ADC_INTERFACE, PROG_DATA_DECODE and PROG_DATA_LATCH are all going to be additional VHDL files. I may need to see them.
CLKINT is an ACTEL specific library macro which is used to promote an internal logic signal (rather than an input pin) to a global or clock distribution network. I do not know if there is a Xilinx equivalent, but you may not need one as the Xilinx tool should be capable of auto-promotion of nets. If not it will be possible to input some form of constraint to force it (I have not used Xilinx for a long time)
If we assume that the first three components do not use any Actel specific components then:
Delete the two lines
LIBRARY A54SXA;
USE A54SXA.ALL;
delete the following:
COMPONENT CLKINT
PORT (
A : IN STD_ULOGIC;
Y : OUT STD_ULOGIC);
END COMPONENT;
As I cannot see all the file I will have to generalise a bit but further down you will see something similar to this:
U4: CLKINT
PORT MAP(
A => Input_Signal,
Y => Output_Signal);
Delete or comment out the above and replace it with:
Output_Signal <= Input_signal; (using the real signal names of course)
We can worry about the function of the CLKINT later. As I said, you probably don't need it anyway
If any of the other three modules have the lines:
LIBRARY A54SXA;
USE A54SXA.ALL;
just delete them.
That should be it, Modelsim should be happy.