amir68
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HELLO i am new member,i have a project about Design of two Low-Power ful ladder cells using GDI structure and hybrid CMOS logic style in my university and i have probelam with designing of this circuits in Hspice.
1:I need 90nm and 0.13um cmos technology library for hspice
2:I do not know how does the ulpd circuit is design and where does the source gate and drain of the each transistor in ulpd mod connect.
please help me.and if u need jurnal for helping say it to me and i will send the jurnal for u.tanks a lot
the image of full adder is shown in
https://obrazki.elektroda.pl/index.php
1:I need 90nm and 0.13um cmos technology library for hspice
2:I do not know how does the ulpd circuit is design and where does the source gate and drain of the each transistor in ulpd mod connect.
please help me.and if u need jurnal for helping say it to me and i will send the jurnal for u.tanks a lot
the image of full adder is shown in
https://obrazki.elektroda.pl/index.php