The specification are:
output frequency:1100MHz ~1650MHz ;
frequency step :1kHz;
switching time:<100us;
spur:<-65dBc;
PN: <-85dBc/Hz@1kHz
<-95dBc/Hz@10kHz
<-105dBc/Hz@100kHz
application: handset(so It's must be very small)
I have designed a 1100MHz~1650MHz frequency synthesizer by two fractional PLL working in pingpong mode to get fast swiching time .But It's too big, and not fit for handset.
Maybe you need use DDS and mixing DDS signal with some LO signal. If your band is too wide, maybe you need divide it into 2 band. So use switch switch between two LO signals.
Maybe you need use DDS and mixing DDS signal with some LO signal. If your band is too wide, maybe you need divide it into 2 band. So use switch switch between two LO signals.
---------- Post added at 03:17 AM ---------- Previous post was at 03:13 AM ----------
I think if adding a DAC on VCO to preset the conrol voltage, May be the swiching time be shorter. could someone give me some experience about this plan? how to add the loop filter output and DAC to the VCO conrol pin? use an low noise OP?
That's not a good idea. You will find the VCO can't lock, it will drift in mormal temperature. The drift maybe caused by TCXO, voltage drift, ground noise, temperature, etc.
Use a DAC to set the inital VTune looks reasonable.However any solution on Board level will be big. You can check @DI' ADF4193. It has 25us settle time. Its phase noise at 100KHz is high and need further optimzation.
Use a DAC to set the inital VTune looks reasonable.However any solution on Board level will be big. You can check @DI' ADF4193. It has 25us settle time. Its phase noise at 100KHz is high and need further optimzation.
ADF4193 may be choice,but the 25 us settle time is during GSM band. from 1100MHz to 1650MHz ,the swiching time has to be checked.
Another problem is that ADF4193 seems designed for passive loop filter,But now I must use an active loop filter,for the VCO tunning voltage is high.Maybe I should check it more.
thanks for your reply!
Some PLLs have "fastlock" pin that makes short circuited the PLL Loop Filter Capacitor.
Because 100us is too fast and if you design with locking time, your PLL Loop Filter will have very wideband and that won't satisfy your PN requirements.
I guess you need a combination of "capacitor switched array VCO", "current and LPF switched fast lock circuit" and "ultra high Reference clock". But I don't know what it is.