I have written VGA controller code but nothing is showing up on the screen

[matrixofdynamism]

I don't know if this forum is the right place to get the code checked but may someone with more experience can give me an advice on what could be wrong with my code. I have written VGA controller in VHDL. At present it should just show gibberish on screen like random colors so I can see that the controller does work. I have a Cyclone II board that I am using with it and an Eizo monitor. When I connect the DSUB cable to my design the monitor says that it is not getting any signal on DSUB.

Here is the code:
-----------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity VGA_controller is
port (
clk : in std_logic;
reset : in std_logic;

R: out std_logic_vector(7 downto 0);
G: out std_logic_vector(7 downto 0);
B: out std_logic_vector(7 downto 0);

Hsync: out std_logic;
Vsync: out std_logic;

-- DAC signals
M1, M2: out std_logic;
sync_n, sync_t: out std_logic;
blank_n: out std_logic

);
end entity;


architecture VGA_controller_architecture of VGA_controller is

constant B_count : integer := 95;
constant C_count : integer := 45;
constant D_count : integer := 640;
constant E_count : integer := 20;

constant P_count : integer := 2;
constant Q_count : integer := 32;
constant R_count : integer := 480;
constant S_count : integer := 14;

constant h_sync_cycle_count : integer := 800;
constant v_sync_cycle_count : integer := 528;

-- state machine variables to set the DAC to RGB mode
type dac_mode_state_type is (ds0,ds1,ds2);
signal dac_mode_current_state, dac_mode_next_state : dac_mode_state_type := ds0;

signal h_sync_count_enable : std_logic := '1';
signal h_sync_count : integer := 0; --range 0 to 800 := 0;

signal v_sync_count_enable : std_logic := '0';
signal v_sync_count : integer := 0; --range 0 to 528 := 0;

begin

-- DAC setup mechanism
PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
dac_mode_current_state <= ds0;
ELSIF rising_edge(clk) THEN
dac_mode_current_state <= dac_mode_next_state AFTER 5 ns;
END IF;
END PROCESS;
PROCESS(dac_mode_current_state)
BEGIN

sync_n <= '0';
m2 <= '0';
m1 <= '0';
sync_t <= '0';

CASE dac_mode_current_state IS


WHEN ds0 =>

dac_mode_next_state <= ds1;

WHEN ds1 =>
sync_n <= '0';
m2 <= '0';
m1 <= '0';
sync_t <= '0';
dac_mode_next_state <= ds2;

WHEN ds2 =>
sync_n <= '1';
m2 <= '0';
m1 <= '0';
sync_t <= '0';
dac_mode_next_state <= ds2;

WHEN others =>
sync_n <= '0';
m2 <= '0';
m1 <= '0';
sync_t <= '0';
dac_mode_next_state <= ds0;

END CASE;

END PROCESS;

-- cycle counters for the hsync and vsync system
process(clk)
begin

if rising_edge(clk) then

Hsync <= '1';
Vsync <= '1';
blank_n <= '1';

if h_sync_count >= 800 then
v_sync_count <= v_sync_count + 1;
h_sync_count <= 0;
else
h_sync_count <= h_sync_count + 1;
end if;
if v_sync_count = 528 then
v_sync_count <= 0;
end if;

if v_sync_count >= P_count+Q_count and v_sync_count <= P_count+Q_count+R_count-1 then
-- Hsync mode

if h_sync_count <= 95 then
Hsync <= '0';
else
Hsync <= '1';
end if;

end if;

if v_sync_count <= P_count then
Vsync <= '0';
else
Vsync <= '1';
end if;

if reset = '0' then
blank_n <= '0';
h_sync_count <= 0;
v_sync_count <= 0;
end if;

end if;

end process;

-- generate RGB data
process(clk, h_sync_count, v_sync_count)
begin

if rising_edge(clk) then

R <= x"00";
G <= x"00";
B <= x"00";

if v_sync_count >= P_count + Q_count + R_count/2 then
G <= x"FF";
end if;

if h_sync_count <= B_count + C_count + D_count/2 then
R <= x"F0";
if v_sync_count >= P_count + Q_count + R_count/2 then
B <= x"0F";
G <= x"F0";
end if;
end if;

end if;

end process;

end architecture;
---------------------------------------------------------------------------------------

And now for the test bench:

library IEEE;
use IEEE.std_logic_1164.all;

entity tb is
end entity;

architecture tb_architecture of tb is

component VGA_controller is
port (
clk : in std_logic;
reset : in std_logic;

R: out std_logic_vector(7 downto 0);
G: out std_logic_vector(7 downto 0);
B: out std_logic_vector(7 downto 0);

Hsync: out std_logic;
Vsync: out std_logic;

-- DAC signals
M1, M2: out std_logic;
sync_n, sync_t: out std_logic;
blank_n: out std_logic

);
end component;

signal clk : std_logic := '0';
signal reset : std_logic := '0';

signal R: std_logic_vector(7 downto 0);
signal G: std_logic_vector(7 downto 0);
signal B: std_logic_vector(7 downto 0);

signal Hsync: std_logic;
signal Vsync: std_logic;

-- DAC signals
signal M1, M2: std_logic;
signal sync_n, sync_t: std_logic;
signal blank_n: std_logic;

signal hsync_count_t : integer := 0;

begin

inst0: VGA_controller
port map (

clk => clk,
reset => reset,

R => R,
G => G,
B => B,

Hsync => Hsync,
Vsync => Vsync,

M1 => M1, M2 => M2,
sync_n => sync_n, sync_t => sync_t,
blank_n => blank_n

);

reset <= '1' after 6000 ns;
clk <= not clk after 20 ns;

process(Hsync, hsync_count_t)
begin
if Hsync'event and Hsync='0' then
hsync_count_t <= hsync_count_t + 1;
end if;
end process;

end architecture;

The simulation seems to be just fine, but I can't see my monitor react at all.

 

[TrickyDicky]

Have you put the dsub pins on a scope to make sure it looks ok? do they meet the timing and voltage specs?

 

[lucbra]

I would assume you are running this on a 800 x 600 screen - why do you count to 528?

 

[matrixofdynamism]

No, it is a 480*640 resolution.