Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

I have IBIS model of an oscillator with input, output, enable signals. How to use it?

Not open for further replies.


Advanced Member level 2
Apr 17, 2011
Reaction score
Trophy points
Activity points
I have an IBIS model of a clock oscillator. I want to find out if there will be high speed effects on the clock signal. I have converted it into a PSpice model for use in Cadence design suite simulation tools. This resulting PSice model has 3 terminals which are input, output and enable. It is derived from IBIS model of a 50MHz oscillator.

An oscillator sources a clock signal. How do I get that effect on this IBIS model in simulation as it does not generate a clock automatically? Do I merely connect an ideal pulse source to the input, tie the enable high permanently and the signal at the output terminal shall be the clock wave as found in the physical device?

What you might be having is IBIS model of I/O buffer (not of oscillator).
You would need to provide 50Mhz clock at input, package parasitics would already be there specified in IBIS model.
You would need to terminate this by connecting TLINE and appropriate load at output, to see any reflections etc.

OK, basically I took the IBIS model and converted it into PSpice. That is how I end with this block with input, output and enable signals. Should have told this in the first post.

Not open for further replies.

Part and Inventory Search

Welcome to