Hi, guys its, me again. I'm still tryning to run a verilog code that I wrote its an OR gate, nothing complicated, when I synthesized it to use it in virtouoso, I wasn't able to find the transistors, what I did was write a code in verilog, synthesize it in Encounter and saving it as GDS2 3to import it to virtuoso, and in virtuoso I wasn't able to se the transisgtors, and the I'm getting the error that I got I mentioned befrore "The referenced cell "or2_1" was not found. The OpenAccess design data was created for this cell without any reference. Ensure that the referenced cell exists and the Lib is defined in library definition file." and I still haven't figured out how to fix it