library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- =============== Interface Description ===============
entity COUNTER_DEC is
port (clock : in std_logic; -- positive edge
reset : in std_logic;
start : in std_logic; -- start process
done_count: out std_logic -- end of the process
);
end COUNTER_DEC;
architecture COUNTER_DEC_RTL of COUNTER_DEC is
-- =============== Signal Definition ===============
signal tmp : std_logic;
signal active : std_logic;
signal counter: std_logic_vector(3 downto 0);
-- =============== Data Movement ===============
begin
START_COUNTER: process ( clock, reset )
begin
if reset = '1' then
counter <= (others => '0');
tmp <= '0';
active <= '0';
elsif (start = '1' or active = '1') then
if clock'event and clock = '1' then
counter <= (counter + '1');
else
counter <= counter;
tmp <= tmp;
end if;
active <= active xor start;
else
counter <= "0000";
tmp <= '0';
active <= '0';
end if;
if counter = "1100" then
tmp <= '1';
counter <= "0000";
active <= '0';
else
tmp <= '0';
end if;
done_count <= tmp;
end process;
end COUNTER_DEC_RTL;