i am implementing sap-1 microprocessor in vhdl.but hav prob

sap microprocessor

i am implementing sap-1 in vhdl.but i cannot make system bus and controller circuit. here is my code of controller.if possible fix the error.i will be very great full

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.all;


entity control_matrix is
port(

clk :in std_logic;
reset: in std_logic;
id_lda :in std_logic;
id_add:in std_logic;
id_sub:in std_logic;
id_out:in std_logic;
id_hlt:in std_logic;
cp_coutut std_logic;
ep_coutut std_logic;
lm_coutut std_logic;
er_coutut std_logic;
l1_coutut std_logic;
e1_coutut std_logic;
la_coutut std_logic;
ea_coutut std_logic;
su_coutut std_logic;
eu_coutut std_logic;
lb_coutut std_logic;
lo_coutut std_logic
);
end control_matrix;
architecture struct of control_matrix is

component ring_test is
port (clk, reset: in bit;
t_state: out bit_vector(5 downto 0));

end component;

component ir_decoder is
port( ip: in std_logic_vector(3 downto 0);
op: out std_logic_vector(4 downto 0)
);
end component;

signal t1_state: std_logic_vector(5 downto 0);
signal ir_deco: std_logic_vector(4 downto 0);

signal state0: std_logic;
signal state1: std_logic;
signal state2: std_logic;
signal state3: std_logic;
signal state4: std_logic;
signal state5: std_logic;

begin
process(clk,reset)
begin
U1: ring_test port map(t_state(0)=>state0,t_state(1)=>state1,t_state(2)=>state2,
t_state(3)=>state3,t_state(4)=>state4,t_state(5)=>state5);
U2: ir_decoder port map();
if reset='1'then
cp_cout<="0";
ep_cout<="0";
lm_cout<="0";
er_cout<="0";
l1_cout<="0";
e1_cout<="0";
la_cout<="0";
ea_cout<="0";
su_cout<="0";
eu_cout<="0";
lb_cout<="0";
lo_cout<="0";

elsif (clk'event and clk='1')then



cp_cout<=state2;
ep_cout<=state2;
lm_cout<=state0 or (id_lda and state3) or (id_add and state3) or (id_sub and state3) ;
er_cout<=state1 or (id_lda and state4) or (id_add and state4) or (id_sub and state4) ;
l1_cout<=state1;
e1_cout<=(id_lda and state3)or (id_add and state3) or (id_sub and state3) ;

la_cout<=(id_lda and state4) or (id_add and state5) or (id_sub and state5);
ea_cout<=id_out and state3;
su_cout<=id_sub and state5;
eu_cout<=(id_add and state5) or (id_sub and state5);
lb_cout<=(id_add and state4) or (id_sub and state4);
lo_cout<=id_out and state3;
end if;
end process;
end struct;

here i also give the code of ir_decoder and ring counter
library ieee;
use ieee.std_logic_1164.all;



entity ir_decoder is
port( ip: in std_logic_vector(3 downto 0);
op: out std_logic_vector(4 downto 0)
);
end ir_decoder;

architecture behv of ir_decoder is
begin



process (ip)
begin



case ip is
when "0001" => op <= "00001";--lda
when "0010" => op <= "00010";--add
when "0011" => op <= "01000";
when "0100" => op <= "00101";
when others => op <= "XXXXX";
end case;

end process;

end behv;

ring counter:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_bit.all;

entity ring_test is
port (clk, reset: in bit;
t_state: out bit_vector(5 downto 0));
end ring_test;

architecture behv of ring_test is
signal IQ : bit_vector(5 downto 0);
signal LIN : bit;
begin
LIN <= not iq(4) and not iq(3) and not iq(2) and not iq(1) and not IQ(0);
process(clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
iq <= "000001";
else
iq <= iq(4 downto 0) & LIN;
end if;
end if;
end process;
t_state <= iq;
end behv;


any one can pls make the port map for this code