Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] hspice veriloge-a problem

Status
Not open for further replies.

admiral_v

Newbie level 6
Joined
Feb 27, 2014
Messages
14
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
87
hii i write this verilog-a for variable capacitor and i test circuit in hspice but capacitor don't change While i expected capacitance change sinusoidal please help me
Code:
`include "constants.vams"
`include "disciplines.vams"
 
module vccap(Cp, Cn, Vp, Vn);
 
    input Vp, Vn;
    inout Cp, Cn;
 
    electrical Cp, Cn, Vp, Vn;
 
    real C;
 
    parameter real C0 = 0;
    parameter real CS = 2.5p;
 
    analog begin 
           
        C =  V(Vp,Vn);
        I(Cp,Cn) <+ C * ddt(V(Cp,Cn)); 
    end
 
endmodule
hspice test :

Code:
.hdl vccap.va
.options post=1

x1 1 2 3 4   vccap 

vi 3 4 sin( 0 1 500k)

.tran 2n 500us

.PROBE tran cap(1,2) cap(1) cap(2) 
.end
 

admiral_v

Newbie level 6
Joined
Feb 27, 2014
Messages
14
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
87
if i connect resistor for test , not variable capacitor show in node 1and 2
r1 1 2 2meg For example
 

admiral_v

Newbie level 6
Joined
Feb 27, 2014
Messages
14
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
87
No one is here to help me?
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top