Re: Hspice simulation problem
Dear hoolish,
I have not simulated your circuit as yet. But the PMOS terminals are nemed wrongly.
The sequence is
drain,gate, source and bulk.
You have source,gate drain and bulk. COrrect it and run the simulation. Ishall also try in mean while
Added after 28 minutes:
Dear Hoolish,
Delete the as,ad,ps,pd from bothnthe ytransistors.
And observe the results
U have for NMOS as=25 ps=20
I have done small modification in them. please simulate now and se
vdd vdd gnd 5V
vgnd gnd 0 dc 0
m1 output clock1 vdd Vdd p15 w=4u l=1.6u m=3 as=21p ad=21p ps=30u pd=30u
m2 output in1 Gnd Gnd n15 w=4u l=1.6u as=6.4p ad=6.4p ps=10u pd=10u
Vclock1 clock1 gnd pulse(0 5 0 1p 1p 180u 400u)
Vin1 in1 gnd sin(1.7 1.5 120)
.option captab
.OP
.Tran 10n 10ms
.option post
.end