Hspice simulation question

[hoolish]

Hspice simulation problem

I use hspice first time.
I make a PMOS and a NMOS inverter circuit. The PMOS's gate is connected to a clock and NMOS connect to a sinewave. So that the output should also be a sinewave which is verified by Cadence. But in Hspice, I find that the output is just a constant voltage with value 2.3V. I feel strange so that I ask help here. The Hspice netlist is as below:

vdd vdd gnd 5V

m1 vdd clock1 output Vdd pmos w=4u l=1.6u
+ ad=0 pd=0 as=25 ps=20
m2 output in1 Gnd Gnd nmos w=4u l=1.6u
+ ad=55 pd=42 as=0 ps=0

Vclock1 clock1 gnd pulse(0 5 0 1p 1p 180u 400u)
Vin1 in1 gnd sin(1.7 1.5 120)

.OP
.Tran 40us 120ms
.option post
.END

 

[zwei78]

I think you must write " Vvdd vdd gnd 5V"

 

[hoolish]

I have tried Vvdd vdd gnd 5V.
The result does not change.

 

[willyboy19]

The actual cause of the problem is that you have a 'floating' ground node. You need to define node 'gnd' as:

vgnd gnd 0 0

Try this and this simple inverter should work!

 

[hoolish]

I have added, no change. I included all my hspice file here now:


Example of an HSpice
.param supply=5v
Vvdd vdd gnd 'supply'
vgnd gnd 0 0


m1 vdd clock1 out1 Vdd pfet w=4u l=1.6u
+ ad=0 pd=0 as=25 ps=20
m2 gnd in1 out1 Gnd nfet w=4u l=1.6u
+ ad=55 pd=42 as=0 ps=0

Vclock1 clock1 gnd pulse(0 5 0 1p 1p 180u 400u)
Vin1 in1 gnd sin(1.7 1.5 120)

.MODEL nfet NMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 3.12E-8
+XJ = 3E-7 NCH = 7.5E16 VTH0 = 0.5467455
+K1 = 0.9227937 K2 = -0.0714388 K3 = 3.9081179
+K3B = -2.8894475 W0 = 3.091859E-6 NLX = 1E-8
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 0.9220554 DVT1 = 0.3313267 DVT2 = -0.2563813
+U0 = 635.832494 UA = 1.036105E-9 UB = 2.718522E-18
+UC = 1.239422E-11 VSAT = 1.107997E5 A0 = 0.6236474
+AGS = 0.0961052 B0 = 1.922604E-6 B1 = 5E-6
+KETA = -5.322446E-3 A1 = 0 A2 = 1
+RDSW = 3E3 PRWG = -0.0330566 PRWB = -0.0354994
+WR = 1 WINT = 6.796811E-7 LINT = 2.521522E-7
+XL = 0 XW = 0 DWG = -1.694043E-8
+DWB = 1.928021E-8 VOFF = -0.0253455 NFACTOR = 0.6517199
+CIT = 0 CDSC = 0 CDSCD = 0
+CDSCB = 6.121208E-5 ETA0 = -0.4920653 ETAB = -0.1283053
+DSUB = 0.5418256 PCLM = 1.2987638 PDIBLC1 = 9.657234E-3
+PDIBLC2 = 2.131921E-3 PDIBLCB = 0.1 DROUT = 0.0625749
+PSCBE1 = 2.162225E9 PSCBE2 = 5E-10 PVAG = 0.2051476
+DELTA = 0.01 RSH = 52.7 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 1.76E-10 CGSO = 1.76E-10 CGBO = 1E-9
+CJ = 2.811181E-4 PB = 0.99 MJ = 0.5481751
+CJSW = 1.436446E-10 PBSW = 0.99 MJSW = 0.1
+CJSWG = 6.4E-11 PBSWG = 0.99 MJSWG = 0.1
+CF = 0 )
*
.MODEL pfet PMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 3.12E-8
+XJ = 3E-7 NCH = 2.4E16 VTH0 = -0.8476404
+K1 = 0.4513608 K2 = 2.379699E-5 K3 = 13.3278347
+K3B = -2.2238332 W0 = 9.577236E-7 NLX = 7.203971E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 1.0660207 DVT1 = 0.379073 DVT2 = -0.0871059
+U0 = 236.8923827 UA = 3.833306E-9 UB = 1.487688E-21
+UC = -1.08562E-10 VSAT = 1.223676E5 A0 = 0.2498126
+AGS = 0.3763193 B0 = 4.36682E-6 B1 = 5E-6
+KETA = -1.620401E-3 A1 = 0 A2 = 0.364
+RDSW = 3E3 PRWG = 0.0999554 PRWB = -0.1524827
+WR = 1 WINT = 7.565065E-7 LINT = 1.052472E-7
+XL = 0 XW = 0 DWG = -2.13917E-8
+DWB = 3.857544E-8 VOFF = -0.0877184 NFACTOR = 0.2508342
+CIT = 0 CDSC = 2.924806E-5 CDSCD = 1.497572E-4
+CDSCB = 1.091488E-4 ETA0 = 0.27103 ETAB = 3.713138E-4
+DSUB = 0.2873 PCLM = 1E-10 PDIBLC1 = 4.383388E-4
+PDIBLC2 = 1.515877E-3 PDIBLCB = -1E-3 DROUT = 9.98811E-4
+PSCBE1 = 3.518672E9 PSCBE2 = 5.279076E-10 PVAG = 15.0001499
+DELTA = 0.01 RSH = 73.2 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 2.09E-10 CGSO = 2.09E-10 CGBO = 1E-9
+CJ = 3.003814E-4 PB = 0.8 MJ = 0.4429957
+CJSW = 1.707914E-10 PBSW = 0.8 MJSW = 0.1051155
+CJSWG = 3.9E-11 PBSWG = 0.8 MJSWG = 0.1051155
+CF = 0 )

.OP
.Tran 40us 20ms
.option post
.END

 

[always@smart]

i got the result in attachment, not sure if it is wat u expected?

the output was a square wave then i removed

vgnd gnd 0 0

and got this result.



pls check

 

[ambreesh]

Re: Hspice simulation problem

Dear hoolish,
I have not simulated your circuit as yet. But the PMOS terminals are nemed wrongly.
The sequence is
drain,gate, source and bulk.
You have source,gate drain and bulk. COrrect it and run the simulation. Ishall also try in mean while

Added after 28 minutes:

Dear Hoolish,
Delete the as,ad,ps,pd from bothnthe ytransistors.
And observe the results
U have for NMOS as=25 ps=20
I have done small modification in them. please simulate now and se

vdd vdd gnd 5V
vgnd gnd 0 dc 0

m1 output clock1 vdd Vdd p15 w=4u l=1.6u m=3 as=21p ad=21p ps=30u pd=30u

m2 output in1 Gnd Gnd n15 w=4u l=1.6u as=6.4p ad=6.4p ps=10u pd=10u


Vclock1 clock1 gnd pulse(0 5 0 1p 1p 180u 400u)
Vin1 in1 gnd sin(1.7 1.5 120)
.option captab
.OP
.Tran 10n 10ms
.option post
.end