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hspice simulation issue in VCO

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Full Member level 3
Mar 21, 2002
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hspice warning negative

I have got a problem with hspice simulation of VCO.

When I am simulating netlist as below, the simulation results will be incorrect.
As we can see, the resistor R1 & R2 is the loss resistor of spiral inductor.
If we tune their value to 0, the simulation results will be very weird. That is:
the voltage at output node will be greater than the supply voltage.

Also, the .lis file sometimes contains lines as follow:

"warning" negative-mos conductance =......

Can anyone explain it for me?

* Generated on Dec 31 01:38:15 2002.
MN2 NET21 NET23 0 0 N18 L=500E-9 W=235E-6 M=1.0
MN1 NET23 NET21 0 0 N18 L=500E-9 W=235E-6 M=1.0
C0 NET23 NET9 1E-12 M=1.0
C1 NET21 NET9 1E-12 M=1.0
L1 NET3 NET6 3E-9 M=1.0
L2 NET3 NET22 3E-9 M=1.0
R3 0 NET9 3E6 M=1.0 **DC path
R1 NET6 NET23 20.0 M=1.0 **loss resistor of spiral inductor
R2 NET22 NET21 20.0 M=1.0 **loss resistor of spiral inductor
R5 VCC NET3 300.0 M=1.0 **resistor cause voltage drop
VDD VCC 0 2.5
* Include files
* End of Netlist
.TRAN 1.0000 5.0000 START= 0.
.TEMP 25.0000

vco + hspice


It is not werid to have voltages greater than the supply rails when you have inductors in your circuit. More common even, if the series parasitic resistors are zero, which means that the quality factor is infinite. Remember that the inductor keeps the current through it continuous, which can make a huge voltage among the terminals. Have you never tried a big inductor in parallel with a 1.5V battery and suddenly disconnected the batery, holding the inductor terminals in contac with you??

The negative conductance can arise from a self heating of the transistor. It depends on the model you're using. If it is due to self heating, when your transitor is driven by a big GVO (Vg-Vth), some models take into account the increase on the substrate temperature givin rise to a reduction of Id as Vd increases. That means that the output conductance becomes negative.

What model do you use?

hspice vco

I used to think this was weird also, but now I look at it like this:

the inductor/capacitor form a tank circuit... and it is very literally that, a tank that stores. This is what allows it to get above the supply voltage, storage. So lets say that you store some amount during one cycle, then next cycle, because your gain is greater than one, you have all the energy you had previously, plus a little more. And so on, and so on. It is only the resistive and nonlinear part of the circuit that ends up limiting this amplitude.

There are other circuits called "pump" circuits that use a somewhat similar method of getting "dc" voltages above the supply. They pump a current onto a capacitor then switch it to add to the supply. As long as it is driving a large impedance (i.e. a capacitive load) then it isn't really supplying much current and the power lost is minimal.

Hope this helps. The above explanation was also good.

hspice voltage controlled oscillator

Thanks for you two's reply and help.

Still, I got one problem that why the limiting effect of the mosfet doesn't work?

should not the output voltage of the mosfets be limited due to the limiting effect?

hspice vco gain

It is common for a tuned circuit to have voltage at some nodes higher than the supply voltage.

If you transistor have some hard clamping mechanism (e.g. breakdown), it is possible that the node voltage of the transistor terminal is clamped. However, the output node of the circuit may still go over the supply voltage.

vco simulation netlist

I agree. Imagine that the transistor is an nfet, and its drain is going above the supply voltage. Well, except for breakdown, this isn't a problem. This happens at different voltages depending on the process, but in, oh lets say .15u TSMC digital CMOS your digital 1.2v nfets can have up to (supposedly) 4 volts across the gate to channel without damaging anything. The analog 3.3v fets have significantly more room. The only things you really have to look out for is forward biasing diodes and such.

For instance in one particular oscillator design where varactors were used, when the oscillation amplitude became larger than a certain amount, it forward biased the varactor diodes and seriously degraded phase noise. You can imagine something like this also happening if your nfet drain went too far below ground (enough to forward biase the junction diodes). Your ESD would kick in, but it would be too late for your poor phase noise.

Here is my suggestion. Do a sweep of your fets. The old I vs. VDS plot. This will show you exactly how your fets are affected by the VDS across them. Also do the I vs. VDS plots for different VGS's. Take that VDS to a number high enough to see breakdown occuring. Then you'll have a real idea what your transistors look like in what voltage ranges.

hope this helps.

warning negative-mos conductance

It give me a lot idea about VCO from your reply.

Also, your style and your image make me remember Razavi BH.

Thank you!

**warning** negative-mos conductance


What a reply from electronlover!!!!

That's the wonderful of elektroda: to have guys like these ready to give a hand!!!!

The only thing I must point to is that it depends a lot on the model you're using if breakdown of any other non-linear effect limiting the oscillation amplitude have been well modelled.

It would help a lot having a test wafer at hand to test such effects. As you are using 0.5um long transistors, I can inffer that this is the feature length of your technology. This means that BVO must be quite high. My advise (if any;-) would be that you should try to accurately estimate the actual parasitic resistance of your (integrated?) inductors.

See you


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