Hello everyone,
I want to go from HSpice netlist to Layout and want to calculate area.
Could anybody tell me please the exact flow (means procedure) & tools required in that flow.
Hello everyone,
I want to go from HSpice netlist to Layout and want to calculate area.
Could anybody tell me please the exact flow (means procedure) & tools required in that flow.
if you only want to find the area: tools like Tanner ( S-Edit ) can convert SPICE (HSpice, PSpice, TSpice, doesn't matter ) to Verilog/VHDL, from where you can use standard flow to calculate the area.
why you don't estimate the area? you can put say ~800λ² for each transistor that you've. right?