[SOLVED] Hspice netlist to Layout ...

[skamthey]

hspice netlist

Hello everyone,
I want to go from HSpice netlist to Layout and want to calculate area.
Could anybody tell me please the exact flow (means procedure) & tools required in that flow.

Thanks & Regards
SKamthey

 

[tariq786]

convert spice netlist to layout

I dont think you can do it automatically. You need to do it manually.

I hope some senior members can shed some more light.

 

[ahmadyan]

converting spice netlist to layout

Hello everyone,
I want to go from HSpice netlist to Layout and want to calculate area.
Could anybody tell me please the exact flow (means procedure) & tools required in that flow.

Thanks & Regards
SKamthey

if you only want to find the area: tools like Tanner ( S-Edit ) can convert SPICE (HSpice, PSpice, TSpice, doesn't matter ) to Verilog/VHDL, from where you can use standard flow to calculate the area.
why you don't estimate the area? you can put say ~800λ² for each transistor that you've. right?

 

[kumarghz]

netlist hspice

You can use Tanner EDA tool (L-edit) with Standard Place and Route (SPR) option.