iamxo
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I'm simulating an 1k SRAM, with spice netlist.
At first, I use hsim(due to its high speed) and get the expected result.
However, when I change the tool to Hspice(more accurate than hsim), the result was totally wrong. the input clock to the SRAM through the driver buffer is no clock waveform, just waveform like steps.
but I find that the hspice converges successfully.
So, anyone meets the same problem or like that?? Give some advice or explainations, I have searched in google and gets nothing useful.
Thanks in advance.
At first, I use hsim(due to its high speed) and get the expected result.
However, when I change the tool to Hspice(more accurate than hsim), the result was totally wrong. the input clock to the SRAM through the driver buffer is no clock waveform, just waveform like steps.
but I find that the hspice converges successfully.
So, anyone meets the same problem or like that?? Give some advice or explainations, I have searched in google and gets nothing useful.
Thanks in advance.