xyy
Newbie level 2
Hi, recently I tried to simulate d-flip flop in HSPICE. I follow steps from this website (https://wenku.baidu.com/view/7843ef0bbb68a98271fefac4). I try to implement it in my netlist and it worked except for hold rise. I cant figure what's the problem, is it my code or the d-flip flop is acting weird.
Here's the screenshot of the waveforms:
And my HSPICE code for bisection method:
So my question, is it my d-flip flop got problem or my code? Is there any way to maintain the output voltage so that it stays at high until end?
Thanks.
Here's the screenshot of the waveforms:
And my HSPICE code for bisection method:
Code:
.tran 1f 10n sweep optimize=opt1 result=clk_to_q model=optmod
.model optmod opt method=passfail
.param t_hold=opt1(1.0ns, '-1.0*t_setup+trf_data+1fs', 1.0ns)
.measure tran clk_to_q
+ trig v(CK) val='v(vdd)/2.0' rise=1
+ targ v(Q) val='v(vdd)/2.0' rise=1
+ pushout_per=0.1 upper
So my question, is it my d-flip flop got problem or my code? Is there any way to maintain the output voltage so that it stays at high until end?
Thanks.