# HSPICE D Flip Flop hold rise (it rises and fall back!)

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#### xyy

##### Newbie level 2
Hi, recently I tried to simulate d-flip flop in HSPICE. I follow steps from this website (https://wenku.baidu.com/view/7843ef0bbb68a98271fefac4). I try to implement it in my netlist and it worked except for hold rise. I cant figure what's the problem, is it my code or the d-flip flop is acting weird.

Here's the screenshot of the waveforms:

And my HSPICE code for bisection method:
Code:
.tran 1f 10n sweep optimize=opt1 result=clk_to_q model=optmod
.model optmod opt method=passfail
.param t_hold=opt1(1.0ns, '-1.0*t_setup+trf_data+1fs', 1.0ns)

.measure tran clk_to_q
+ trig v(CK) val='v(vdd)/2.0' rise=1
+ targ v(Q) val='v(vdd)/2.0' rise=1
+ pushout_per=0.1 upper

So my question, is it my d-flip flop got problem or my code? Is there any way to maintain the output voltage so that it stays at high until end?

Thanks.

#### gs65

##### Member level 1
hi,
i guess some problem with your code, send the code of d flipflop. the code which you have attached does not contain line related to d flipflop

#### FvM

##### Super Moderator
Staff member
At first sight, it looks like a trivial setup or hold time violation. Did you check with setting d earlier and holding it longer?

#### xyy

##### Newbie level 2
The problem is the setup time. I use pushout 1% during simulation of setup time, then when I used back value I get to calculate hold time the output will be same as the picture.

So I ran the simulation again without any pushout, means the max time for setup time. Used that value for hold time which gave me the stable output. :-D

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