amihomo
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how to give inputs to vhdl
Hi
I've been working with HDL simulation softwares in Windows environment until recently that I want to switch to Linux environment. I've installed VHDL simulators like FreeHDL, GVHDL and ... in my Linux Fedora core 6. Everything went OK in writing VHDL code , compiling it and running the simulation,but i don't know how to give the input waveforms of the simulation to the simulator.
For example, to see the output of the simulation a half-adder VHDL code ,how can I give the input bits to the the running simulation?
any idea is welcome:?::?:
Hi
I've been working with HDL simulation softwares in Windows environment until recently that I want to switch to Linux environment. I've installed VHDL simulators like FreeHDL, GVHDL and ... in my Linux Fedora core 6. Everything went OK in writing VHDL code , compiling it and running the simulation,but i don't know how to give the input waveforms of the simulation to the simulator.
For example, to see the output of the simulation a half-adder VHDL code ,how can I give the input bits to the the running simulation?
any idea is welcome:?::?: