Howto check for 'Z' value of a signal?

[ripperx2]

Hello,
I have a state machine that should switch on an external input signal. My problem is that the input signal maybe not driven by any device, so it's value is 'Z'. How can I avoid that my state machine switches to an undefined/unintended state? It is possible to check for 'Z' values in a synthesizeable code?
In RTL simulation that is not a problem but for gatelevel simulation and in the FPGA this problem could crash my design.
Thanks for your help!

 

[std_match]

With a pull-up or pull-down resistor you can set the input to the "inactive" state when it isn't driven.

If you want to see the difference between "driven inactive" and "unconnected inactive" you need a more complex solution.

 

[ripperx2]

Yes, a pull-up would help me, but the circuit board design is already done and my CPLD can not integrate a pull-up resistor in the IO buffer. Please can you point me to a solution to detect the "unconnected inactive" state?

 

[std_match]

To detect "unconnected" in a good way you need a hardware change, but in this case it would be better to add the pull-up instead.

I think the best solution depends on the project. How many boards do you build? Is it for a commercial product that you will sell?

If the number of boards is small, maybe you can add a pull-up as a hardware fix?

If you really need to solve it without a hardware change, you could try to activate the output driver on the pin with short pulses of the "inactive" level. Because of capacitance etc the level will change slowly if the pin is not driven. This means that you can sample the input a certain time after a pulse. If it isn't driven, you will see the inactive level.

If the input is driven active, you will have contention during the pulses. Use the weakest possible driver for the pulses. This is an "ugly" solution which can't be used for all projects.

 

[ripperx2]

my altera MAxII CPLD has internal pull-ups
But when I activate the pull-up for my signal, this is not accounted in the gate level simulation. Do you have any ideas why?

edit:
I found a solution: Do Altera simulation models support the programmable internal weak pull up resistor?