how write a Look Up Table

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haneet

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hi frndz,

Can you guyz tell me how to write a Look Up Table in verilog? I know the method of using Case statement and writing. But, is there a short cut where we can write the values?
 

Large Look Up Tables are really ROM memories. You can instantiate a memory in verilog and then give each memory location an initial condition in the test bench. I have also loaded these testbench memories from an external file in the test bench.
In real FPGAs you have to use RAM, since ROM is not available.
 

Is the ROM for any FPGA...?
Your FPGA tool, supposing Xilinx ISE must have applications(core generator) to generate it automatically...
 

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