how to write the top module in verilog and to burn in sp2?

[inevitablewish]

hello.

i am using spartan2 board. i can write verilog codes for different devices but i dont know how to write the top module that calls the cpld module and instantiate our inputs and outputs to the cpld module.

i have some codes that run without problem, like the one i have attached. i have added UCF file, CPLD file and wrote vtop module on top of my code module. please help me out. i will be realy grateful. i have obsession to learn digital designs but.... such problems are troubling me alot.

waiting for the help

regards


////////////////////////////////////////////////////////
how to write this vtop module and how to write the calling function cpld_control?

module vtop(CLK,A,CPLD_CLK,CS,D,OE,WE);
input CLK;
output [5:0]A;
output CPLD_CLK;
output CS;
output[7:0]D;
output OE;
output WE;
wire [7:0]SUM;
wire [7:0]AA,BB;
wire c_in;
wire C_out;
wire c4;

fulladd4 fa0 (SUM[3:0],c4,AA[3:0],BB[3:0],c_in);
fulladd4 fa1 (SUM[7:4],C_out,AA[7:4],BB[7:4],c4);
CPLD_control C0(.CLK(CLK),.leds_low(C_out),.seg_low(SUM[7:0]),.CS(CS),.OE(OE),.WE(WE),.CPLD_CLK(CPLD_CLK),.A(A[5:0]),.buttons_high(AA[7:0]),.buttons_low(c_in),.switches(BB[7:0]),.D(D[7:0]));

endmodule

module fulladd(sum,c_out,a,b,c_in);
output sum,c_out;
input a,b,c_in;
wire s1,c1,c2;

////////////////////////////////////////

xor(s1,a,b);
and(c1,a,b);
xor(sum,s1,c_in);
and(c2,s1,c_in);
or(c_out,c2,c1);
endmodule

//////////////////////////////////////////

module fulladd4(sum,c_out,a,b,c_in);
output [3:0]sum;
output c_out;
input [3:0]a,b;
input c_in;
wire c1,c2,c3;

////////////////////////////////////////

fulladd fa0 (sum[0],c1,a[0],b[0],c_in);
fulladd fa1 (sum[1],c2,a[1],b[1],c1);
fulladd fa2 (sum[2],c3,a[2],b[2],c2);
fulladd fa3 (sum[3],c_out,a[3],b[3],c3);
endmodule