How to write the test bench for the following Bidirectional buffer code

[vijaymarine]

module bidir(dio,clk,rst);
input clk,rst;
inout [15:0]dio;
wire [15:0]dout;
wire oe;
reg [15:0]inreg;
assign dio=oe? dout:16'hzzzz;
always @(posedge clk)
if(rst)
inreg<=16'h0000;
else
inreg<=dio;
endmodule

 

[FvM]

As shown, the module is functionless and doesn't generate any output. In so far, there's no need or usage for a test bench.