Oct 21, 2005 #1 T tarkyss Full Member level 6 Joined Aug 1, 2005 Messages 340 Helped 26 Reputation 52 Reaction score 8 Trophy points 1,298 Location China Activity points 4,162 how to write aggregate in vhdl b=a{1'b1}; a is a constant defined with 'define b is std_logic_vector for example a=4 then b=1111
how to write aggregate in vhdl b=a{1'b1}; a is a constant defined with 'define b is std_logic_vector for example a=4 then b=1111
Oct 23, 2005 #2 S Samer El-Saadany Junior Member level 1 Joined Mar 11, 2005 Messages 19 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,281 Activity points 1,478 I think this would work if a is a constant predefined in a package or something signal b : std_logic_vector (a-1 downto 0); for i in 0 to a-1 loop b(i)<='1'; end loop; hope it would help;-)
I think this would work if a is a constant predefined in a package or something signal b : std_logic_vector (a-1 downto 0); for i in 0 to a-1 loop b(i)<='1'; end loop; hope it would help;-)
Oct 23, 2005 #3 V vomit Full Member level 2 Joined Jun 14, 2002 Messages 148 Helped 14 Reputation 28 Reaction score 4 Trophy points 1,298 Activity points 1,527 As mentioned above, you should use the constant a in the definition of b: signal b : std_logic_vector (a-1 downto 0); Then there is no need anymore to use a, you can just write: b <= (others=>'1'); Look for "aggregate" in any good VHDL tutorial.
As mentioned above, you should use the constant a in the definition of b: signal b : std_logic_vector (a-1 downto 0); Then there is no need anymore to use a, you can just write: b <= (others=>'1'); Look for "aggregate" in any good VHDL tutorial.
Oct 23, 2005 #4 P presto Member level 1 Joined Nov 26, 2001 Messages 39 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 279 or simply signal b : std_logic_vector(a-1 downto 0) := (others =>'1');