what does the memory module look like
Based on what you said, here is the answer:
Below is a "RAM" and a "RAM_TB" written in VHDL. Copy it, understand it and simulated. Let me know if you have anymore questions.
-- *****************************************************************
-- ram.vhd
-- writing data to the ram at a certain address and reading back the
-- same data from the same address
--
-- Design Engineer: Tony Andonie
--
-- Start date: June 28, 2002
-- Revision dates:
--
-- *******************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ram is
port (
data_in : in unsigned(8 - 1 downto 0); -- 8 bit data
address : in unsigned(8 - 1 downto 0):= (others => '0'); -- 8 bit add
we : in std_logic; -- write enable
data_out : out unsigned(8 - 1 downto 0)
);
end ram ;
architecture behav of ram is
type mem_type is array (2**8 downto 0) of unsigned(8 - 1 downto 0);
signal mem : mem_type;
begin
memory : process (we,address,mem,data_in)
begin
if (we = '1') then
mem(to_integer(address)) <= data_in; -- write
end if ;
data_out <= mem(to_integer(address)); -- read
end process memory;
end behav;
-- *******************************************************************
-- ram_tb.vhd
-- this file will test the ram
--
-- Design Engineer: Tony Andonie
--
-- start date:
-- revision dates:
--
-- *******************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_ram is
end tb_ram;
architecture behav of tb_ram is
component ram
port(
data_in : in unsigned ( 8 - 1 downto 0 );
address : in unsigned ( 8 - 1 downto 0 );
we : in std_logic ;
data_out : out unsigned ( 8 - 1 downto 0 )
);
end component;
constant period : time := 10 ns;
signal clk : std_logic;
signal w_data_in : unsigned ( 8 - 1 downto 0 );
signal w_address : unsigned ( 8 - 1 downto 0 );
signal w_we : std_logic ;
signal w_data_out : unsigned ( 8 - 1 downto 0 );
begin
u1 : ram port map (
data_in => w_data_in,
address => w_address,
we => w_we,
data_out => w_data_out
);
clk <= not clk after period/2;
stimuli : process
begin
w_data_in <= "00000000";
w_address <= "00000010";
w_we <= '1';
wait for period;
wait;
end process stimuli;
end behav;