How to write memory module in VHDL?

[V]

I am new in VHDL.
I want to know how to write a memory module, I don't have any idea on coding the memory module by VHDL.
Memory module what i mean is, it is used for save a standard length of the incoming signal, and also the signal should be on hold, during they are saving in the memory.

thank you very much.

 

[revolt]

vhdl memory module

What memory u want to use? A FIFO, shift register...
What does your data look like? serial or parallel data.
How fast is the data?

Take a look into the guides from the FPGA vendor u want to implement your design. There you get information how to infer your memory in vhdl.

e.g.: Xilinx: https://www.xilinx.com/support/sw_manuals/xilinx7/download/lib.zip

 

[Renjith]

what does a memory module look like

which tools r u using?
templates in the tool will give an idea abt modelling a ram or rom or shift register using vhdl.

else, u plz detail ur requirement.
ur explanation was not clear in making a picture for ur requirement.

 

[fields]

tony andonie, baltimore

you want to write a model or a module?
Normally RAM/ROM for digital designer is a
hard-macro , so you need to do is write a ram/rom controller,unless you want to write a model to test your controller.
if you just want to test in FPGA, you can use their IP(LPM_RAM,LPM_ROM,dp_ram... for @ltera)

 

[adap]

what does memory module look like?

Have a look at
https://www.opencores.org/browse.cgi/by_category?filter1=&filter2=

various memory modules are implemented there.

 

[andonie12]

what does the memory module look like

Based on what you said, here is the answer:

Below is a "RAM" and a "RAM_TB" written in VHDL. Copy it, understand it and simulated. Let me know if you have anymore questions.

-- *****************************************************************
-- ram.vhd
-- writing data to the ram at a certain address and reading back the
-- same data from the same address
--
-- Design Engineer: Tony Andonie
--
-- Start date: June 28, 2002
-- Revision dates:
--
-- *******************************************************************

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ram is

port (

data_in : in unsigned(8 - 1 downto 0); -- 8 bit data
address : in unsigned(8 - 1 downto 0):= (others => '0'); -- 8 bit add
we : in std_logic; -- write enable
data_out : out unsigned(8 - 1 downto 0)

);

end ram ;

architecture behav of ram is

type mem_type is array (2**8 downto 0) of unsigned(8 - 1 downto 0);
signal mem : mem_type;

begin
memory : process (we,address,mem,data_in)
begin

if (we = '1') then
mem(to_integer(address)) <= data_in; -- write
end if ;

data_out <= mem(to_integer(address)); -- read

end process memory;
end behav;

-- *******************************************************************
-- ram_tb.vhd
-- this file will test the ram
--
-- Design Engineer: Tony Andonie
--
-- start date:
-- revision dates:
--
-- *******************************************************************

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tb_ram is
end tb_ram;

architecture behav of tb_ram is

component ram

port(

data_in : in unsigned ( 8 - 1 downto 0 );
address : in unsigned ( 8 - 1 downto 0 );
we : in std_logic ;
data_out : out unsigned ( 8 - 1 downto 0 )

);

end component;


constant period : time := 10 ns;

signal clk : std_logic;
signal w_data_in : unsigned ( 8 - 1 downto 0 );
signal w_address : unsigned ( 8 - 1 downto 0 );
signal w_we : std_logic ;
signal w_data_out : unsigned ( 8 - 1 downto 0 );

begin

u1 : ram port map (

data_in => w_data_in,
address => w_address,
we => w_we,
data_out => w_data_out

);

clk <= not clk after period/2;

stimuli : process
begin
w_data_in <= "00000000";
w_address <= "00000010";
w_we <= '1';

wait for period;
wait;
end process stimuli;

end behav;

 

[V]

memory module design

Thank you all of you~

I want to ask andonie
what the following statements means:

type mem_type is array (2**8 downto 0) of unsigned(8 - 1 downto 0);
signal mem : mem_type;

mem(to_integer(address)) <= data_in; -- write

Really thanks for your kindly help.

 

[andonie12]

Re: memory module

V,


Do the following:

1) Take the below updated Designs "ram.vhd" and "ram_tb.vhd" compile them and simulate them using Modelsim

2) type mem_type is array (2**8 downto 0) of unsigned(7 downto 0);
signal mem : mem_type;

a) (2**8 downto 0) means that 2^8 which is 256 ram deep
b) (7 downto 0) means that the ram is 8 bits wide
c) mem_type means you declaring the memory


3) mem(to_integer(address)) <= data_in;
it means that you are writing data_in at a certain address and that address is only integer numbers. " see the testbench" for details. if you have furthur questions feel free to call me after 7:00 pm at (619) 206-6183

Good luck

-- ******************************************************************
-- Company: N/A
-- Project: ram
-- File Name: ram.vhd
-- Engineer: Tony Andonie
--
-- Start Date: April 8, 2005
-- Revision Dates:
--
-- Description: writing data to the ram at a certain address and reading back the
-- same data from the same address
--
-- *******************************************************************


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ram is
port (

data_in : in unsigned(7 downto 0);
address : in unsigned(7 downto 0);
we : in std_logic;
data_out : out unsigned(7 downto 0)
);
end ram;

architecture behv of ram is

type mem_type is array (2**8 downto 0) of unsigned(7 downto 0);
signal mem : mem_type;

begin

memory: process (we,address,mem,data_in)
begin

if (we = '1') then
mem(to_integer(address)) <= data_in; -- write
end if ;

data_out <= mem(to_integer(address)); -- read

end process memory;


end behv;



-- *****************************************************************
-- Company: N/A
-- Project: ram
-- File Name: ram.vhd
-- Engineer: Tony Andonie
--
-- Start Date: April 8, 2005
-- Revision Dates:
--
-- Description: ram testbench
--
--
-- ********************************************************************

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ram_tb is
end ram_tb;

architecture behv of ram_tb is

component ram
port(
data_in : in unsigned(7 downto 0);
address : in unsigned(7 downto 0);
we : in std_logic ;
data_out : out unsigned (7 downto 0)
);
end component;


signal w_data_in : unsigned(7 downto 0):= (others => '0');
signal w_address : unsigned(7 downto 0):= (others => '0');
signal w_we : std_logic:= '0';
signal w_data_out : unsigned(7 downto 0):= (others => '0');

begin

u1_ram: ram port map (

data_in => w_data_in,
address => w_address,
we => w_we,
data_out => w_data_out
);

main: process
begin


-- ******************************************************************
-- write to the ram
--
-- ******************************************************************

-- first cycle
wait for 10 ns;
w_address <= "11000011";
wait for 10 ns;
w_we <= '0';
w_data_in <= "11111111";
wait for 10 ns;
w_we <='1';
wait for 4000 ns;
wait;

end process main;

end behv;