library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity true_dual_port_ram is
port (clk : in std_logic;
we : in std_logic;
en : in std_logic;
addr1 : in std_logic_vector(5 downto 0);
di1 : in std_logic_vector(15 downto 0);
do1 : out std_logic_vector(15 downto 0));
we2 : in std_logic;
en2 : in std_logic;
addr2 : in std_logic_vector(5 downto 0);
di2 : in std_logic_vector(15 downto 0);
do2 : out std_logic_vector(15 downto 0));
end true_dual_port_ram;
architecture ram_arch of true_dual_port_ram is
type ram_type is array (63 downto 0) of std_logic_vector (15 downto 0);
signal RAM : ram_type;
begin
process (clk)
begin
if clk'event and clk = '1' then
if en = '1' then
if we = '1' then
RAM(conv_integer(addr)) <= di;
else
do <= RAM( conv_integer(addr));
end if;
end if;
end if;
end process;
process (clk)
begin
if clk'event and clk = '1' then
if en2 = '1' then
if we2 = '1' then
RAM(conv_integer(addr)) <= di2;
else
do2 <= RAM( conv_integer(addr));
end if;
end if;
end if;
end process;
end ram_arch;