How to write data to address array of dual port RAM using VHDL?

[cloudz88]

Can some1 gimmi the VHDL coding of....how to write data into the address array??
please....really in need....thanks lotsa

 

[anoop12]

Re: VHDL Dual port Ram

---------------------------------------------------------------------------
MEMORY_WRITE:
process (clock)
begin
if (clock'event and clock=1) then
if ( cs_0 = '1' and we_0 = '1') then
mem(conv_integer(address_0)) <= data_0;
elsif (cs_1 = '1' and we_1 = '1') then
mem(conv_integer(address_1)) <= data_1;
end if;
end if;
end process;
----------------------------------------------------------------------------

 

[cloudz88]

Re: VHDL Dual port Ram

what does it mean by mem(conv_integer(address_0) ???

 

[fasmatikos]

VHDL Dual port Ram

It takes "address_0 " which is an std_logic_vector , converts its equivalent integer and use it as pointer for the mem array...Its pretty much the same as c/c++ programming....................
for example address_0 <= "00100" then
conv_integer(address_0) --> 8
mem(8)<=data_1

Added after 1 minutes:

mem( 8 ) <=data_1

 

[cloudz88]

Re: VHDL Dual port Ram

does i need to do any declaration for the mem??

i notice ppl use "Width -1 downto 0" and "Depth -1 downto 0"

what is the main purpose of that??

 

[vlsi_freak]

Re: VHDL Dual port Ram

Hi

In VHDL there is option to give generic parameter, and i guess this is where you are confused. Generic parameter means, the value with which you can change any where in the design. I will explain it to you with an example.

Suppose you have a bus width of 8 i your design. And after designing your complete project your PM is teling to code it as 16 bit bus, and yupp!!!

You have to change that signal all throught your design. But if you have declared your bus width as generic, you can change it in a single shot.

Its syntax is

entity example is
generic ( bus_width : 8);
port (

);
end entity;

Hope it helps.

Thanks

 

[kedhar]

Re: VHDL Dual port Ram

---------------------------------------------------------------------------
MEMORY_WRITE:
process (clock)
begin
if (clock'event and clock=1) then
if ( cs_0 = '1' and we_0 = '1') then
mem(conv_integer(address_0)) <= data_0;
elsif (cs_1 = '1' and we_1 = '1') then
mem(conv_integer(address_1)) <= data_1;
end if;
end if;
end process;
----------------------------------------------------------------------------

here does the "mem" type or signal?????

 

[TrickyDicky]

Re: VHDL Dual port Ram

here does the "mem" type or signal?????

Both. Its a signal of a custom memory type.

 

[nmg]

Re: VHDL Dual port Ram

the above code is fine, but what if i have to write many data ex.data which is (7 downto 0) into address which is(3 downto 0)?
then what do i do?

 

[FvM]

RAM can be only accessed one memory location per clock cycle, you'll need to generate an address sequence, e.g. by a state machine.

 

[nmg]

hi tnx
but how do i use a state machine?
can you please provide a code for it? please.

 

[K-J]

hi tnx
but how do i use a state machine?

I'm suspecting that you aren't putting forth effort to do this task.

can you please provide a code for it? please.

Outside of asking for people to give you stuff, how much effort are you actually putting into this task? If you post your code, people will provide feedback and critique it for you. As it is, you seem to not want to put forth effort, or are at least giving that appearance.

KJ

 

[nmg]

am sorry i am new to this, well right now the code that i am using is as follows

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity true_dual_port_ram is
  port (clk : in std_logic;
        we : in std_logic;
        en : in std_logic;
        addr1 : in std_logic_vector(5 downto 0);
        di1 : in std_logic_vector(15 downto 0);
        do1 : out std_logic_vector(15 downto 0));
        we2 : in std_logic;
        en2 : in std_logic;

        addr2 : in std_logic_vector(5 downto 0);
        di2 : in std_logic_vector(15 downto 0);
        do2 : out std_logic_vector(15 downto 0));

end true_dual_port_ram;


architecture ram_arch of true_dual_port_ram is

        type ram_type is array (63 downto 0) of std_logic_vector (15 downto 0);
        signal RAM : ram_type;
begin

process (clk)
begin
        if clk'event and clk = '1' then
                if en = '1' then
                        if we = '1' then
                                RAM(conv_integer(addr)) <= di;
                        else
                                do <= RAM( conv_integer(addr));
                        end if;
                end if;
        end if;
end process;

process (clk)
begin
        if clk'event and clk = '1' then
                if en2 = '1' then
                        if we2 = '1' then
                                RAM(conv_integer(addr)) <= di2;
                        else
                                do2 <= RAM( conv_integer(addr));
                        end if;
                end if;
        end if;
end process;


end ram_arch;

 

[FvM]

the code that i am using is as follows

The copy-and-paste product hasn't even been syntax-checked.

Besides trivial syntax errors, it's not clear what you want to achieve.
- write synthesizable VHDL code that describes dual-port hardware RAM of a specific vendor
or
- write a pure simulation model

As far as I see, the code (after correction of syntax errors) won't be synthesized to internal RAM e.g. by the Altera tool, because the Altera Quartus RAM template expects read addresses to be registered. Don't know if it's understood by other tools.

Additional questions about writing multiple addresses:
- full problem specification
- design purpose
- timing diagram
- intended target hardware

 

[nmg]

i am trying to get a pure simulation model along with the address sequence,as you mentioned earlier i can do that by using state machine,but i dont know how.