anilineda
Member level 3
1.i have a simple design in verilog , one of the port is "clk" and i want to provide a 200Mhz to this pin.
how to write a constraint in vivado. i am targeting virtex 7 vc707 board. please write the constraint for me.
2.one more question is(see the table below) , what is this "FPGA pin" and "clock source pin" and please mention the difference and which one should i use in the constraint.
3. There are some sytem clocks aswell as user clocks, when and where these are applied.
Table 1-10:
Clock Connections, Source to FPGA
clock source pin | NET NAME | I/O Standard | FPGA (U1) Pin
U51.5 | SYSCLK_N | LVDS | E18
U51.4 | SYSCLK_P | LVDS | E19
U34.5 | USER_CLOCK_N | LVDS | AL34
U34.4 | USER_CLOCK_P | LVDS | AK34
how to write a constraint in vivado. i am targeting virtex 7 vc707 board. please write the constraint for me.
2.one more question is(see the table below) , what is this "FPGA pin" and "clock source pin" and please mention the difference and which one should i use in the constraint.
3. There are some sytem clocks aswell as user clocks, when and where these are applied.
Table 1-10:
Clock Connections, Source to FPGA
clock source pin | NET NAME | I/O Standard | FPGA (U1) Pin
U51.5 | SYSCLK_N | LVDS | E18
U51.4 | SYSCLK_P | LVDS | E19
U34.5 | USER_CLOCK_N | LVDS | AL34
U34.4 | USER_CLOCK_P | LVDS | AK34