how to write constraint for a clock in vivado suite

1.i have a simple design in verilog , one of the port is "clk" and i want to provide a 200Mhz to this pin.
how to write a constraint in vivado. i am targeting virtex 7 vc707 board. please write the constraint for me.

2.one more question is(see the table below) , what is this "FPGA pin" and "clock source pin" and please mention the difference and which one should i use in the constraint.

3. There are some sytem clocks aswell as user clocks, when and where these are applied.

Table 1-10:
Clock Connections, Source to FPGA


clock source pin | NET NAME | I/O Standard | FPGA (U1) Pin
U51.5 | SYSCLK_N | LVDS | E18
U51.4 | SYSCLK_P | LVDS | E19
U34.5 | USER_CLOCK_N | LVDS | AL34
U34.4 | USER_CLOCK_P | LVDS | AK34

2. *** You should study the vc707 Evaluation board 'User Guide' carefully. ***
For the time being, you may ignore the 'clock source pin'. What is important is the 'FPGA Pin'.
Your clock port in the top-level RTL should be mapped correctly to the 'FPGA Pin' in the XDC file.

1. create_clock -period <period_value_in_nano-sec> [get_ports <clock_port>]
e.g.:

create_clock -period 5 [get_ports clk] <-- 200MHz and your port name is "clk"
set_property IOSTANDARD DIFF_SSTL15 [get_ports {clk}]
set_property PACKAGE_PIN R3 [get_ports {clk}]

3. There are various types of clock sources available in the virtex 7 vc707 board. The table shows 2 such sources.
The 1st clock source is a fixed frequency differential clock source, most probably 200MHz.
The 2nd clock source is a user programmable differential clock source, means that o/p clock frequency can be varied as per need.

Thank you so much,you helped me quickly. the syntax worked fine.

now a little question: vc707 offers 200Mhz clock from the clock generator available on board.
what happens (on the board)if my design demands lessthan 200mhz in some case and a greater than 200mhz in other case. how we workout ?

Use a PLL/MMCM to generate a different frequency, see chap 3 of this document.