how to write Clock Gating in verilog

[lordsathish]

Clock Gating

Why do people suggest to avoid clock gating...?
I came across that if we use clock gating in a module then, we'll not be able to use scan chain in that module. Is it because of that...?

Thanks

 

[ljxpjpjljx]

Re: Clock Gating

it very difficult for us to use scan chain if we use clock gating!

 

[navneetgupta]

Re: Clock Gating

Hello lordsathish,

We can use scan chains with clock gating, only thing which is required is that our clock gating will not block scan chain during testing. There are existing methods defined for doing clock gating without impacting scan chains.

With clock gating there is one more issue: While doing timing checks we need to include extra checks known as clock gating checks.

So in summary, clock gating is widley used technique these days with various applications and can easily be used if we understand its implications.

For details u can search for clock gating circuits & clock gating checks.

Hope it helps.

 

[kumar_eee]

Re: Clock Gating

I heard that the Timing Analysis will be tough if the design has clock gating cells..

 

[navneetgupta]

Re: Clock Gating

"I heard that the Timing Analysis will be tough if the design has clock gating cells.."

Yes you are correct, I have already mentioned that we need extra checks if we do clock gating otherwise it can have severe impacts.
And practically if we handle clock gating properly-TA can be simplified to an extent.

Please also look to the other angle- What is we gaining by doing clock gating. Clock gating in many applications simplify our designs(mainly for multi clock designs) + can be used for saving power.

So as much I feel it is very important to use it.

Added after 4 minutes:

Just one more point:

Whenever u use clock gating you should analyze what you are gaining from it. If you are gaining significant use it otherwise avoid it :!:

In my understanding this is simplest way u can decide for using clock gating ?