parameter RED =3'b000; //if assume as 0 round off ~ 0
parameter YELLOW =3'b001; //if assume as 1.2 round off ~1
parameter GREEN =3'b010; //if assume as 2.1 round off ~ 2
parameter BLUE =3'b011; //if assume as 1.7 round off ~ 2
parameter COKLAT =3'b100; //if assume as 0.2 round off ~ 0
parameter BLACK =3'b101; //if assume as 1.4 round off ~ 1
parameter PURPLE =3'b110; //if assume as 2.4 round off ~ 2
parameter ORANGE =3'b111; //if assume as 0.8 round off ~ 1
i want to make coding which i represent the parameter of 3 bit to a point form integer. after that i want to make a condition if the assume is given then it will trigger to the round off number...
exmple : if i want 3 bit (001) which i assume to be 1.2 will be 1 as output....???plz help me with this coding....??:-(
Q2.5 would be an 8-bit signed fixed point number with the value in decimal calculated by the following
-s*2**2 + m[1]*2**1 + m[0]*2**0 + f[4]*2**-1 + f[3]*2**-1 + f[2]*2**-1 + f[1]*2**-1 + f[0]*2**-1
or..
-s*4 + m[1]*2 + m[0] + f[4]*0.5 + f[3]*0.25 + f[2]*0.125 + f[1]*0.0625 + f[0]*0.03125
therefore if you have a number like 010.11001 that would become:
-0*4 + 1*2 + 0 + 1*0.5 + 1*0.25 + 0*0.125 + 0*0.0625 + 1*0.03125 = 2.78125
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 module decoder( input wire CLK, input wire RESET, output reg[2:0]A, output[6:0]state, output reg[6:0]count ); reg[6:0]decoder_state; reg[6:0]step; //output declaration parameter RED =3'b000; parameter YELLOW =3'b001; parameter GREEN =3'b010; parameter BLUE =3'b011; parameter COKLAT =3'b100; parameter BLACK =3'b101; parameter PURPLE =3'b110; parameter ORANGE =3'b111; //state parameter S0=7'b0000000, S1 =7'b0000001, S2 =7'b0000011, S3 =7'b0000111, S4 =7'b0001111, S5 =7'b0011111, S6 =7'b0111111, S7 =7'b1111111, S8 =7'b1111110, S9 =7'b1111100, S10 =7'b1111000, S11 =7'b1110000, S12 =7'b1100000, S13 =7'b1000000, S14 =7'b0000000, S15 =7'b0001000, S16 =7'b0011000, S17 =7'b0001110, S18 =7'b0111100, S19 =7'b0111110, S20 =7'b1110111, S21 =7'b1111111, S22 =7'b1011111, S23 =7'b1001111, S24 =7'b0011110, S25 =7'b0011100, S26 =7'b0001100, S27 =7'b0010000, S28 =7'b0000000; //COUNT parameter SEC13 =7'b0001101; parameter SEC7 =7'b0000111; assign state=decoder_state; always@(posedge CLK or posedge RESET) begin if(RESET==1) begin decoder_state<=S0; count<=0; end else case(step) 0: if(count<SEC13) begin step<=0; decoder_state<=S0; count<=count+1'b1; end else begin step<=1; decoder_state<=S1; count<=0; end 1: if(count<SEC7) begin step<=1; decoder_state<=S1; count<=count+1'b1; end else begin step<=2; decoder_state<=S2; count<=0; end 2: if(count<SEC7) begin step<=2; decoder_state<=S2; count<=count+1'b1; end else begin step<=3; decoder_state<=S3; count<=0; end 3: if(count<SEC7) begin step<=3; decoder_state<=S3; count<=count+1'b1; end else begin step<=4; decoder_state<=S4; count<=0; end 4: if(count<SEC7) begin step<=4; decoder_state<=S4; count<=count+1'b1; end else begin step<=5; decoder_state<=S5; count<=0; end 5: if(count<SEC7) begin step<=5; decoder_state<=S5; count<=count+1'b1; end else begin step<=6; decoder_state<=S6; count<=0; end 6: if(count<SEC7) begin step<=6; decoder_state<=S6; count<=count+1'b1; end else begin step<=7; decoder_state<=S7; count<=0; end 7: if(count<SEC13) begin step<=7; decoder_state<=S7; count<=count+1'b1; end else begin step<=8; decoder_state<=S8; count<=0; end 8: if(count<SEC7) begin step<=8; decoder_state<=S8; count<=count+1'b1; end else begin step<=9; decoder_state<=S9; count<=0; end 9: if(count<SEC7) begin step<=9; decoder_state<=S9; count<=count+1'b1; end else begin step<=10; decoder_state<=S10; count<=0; end 10: if(count<SEC7) begin step<=10; decoder_state<=S10; count<=count+1'b1; end else begin step<=11; decoder_state<=S11; count<=0; end 11: if(count<SEC7) begin step<=11; decoder_state<=S11; count<=count+1'b1; end else begin step<=12; decoder_state<=S12; count<=0; end 12: if(count<SEC7) begin step<=12; decoder_state<=S12; count<=count+1'b1; end else begin step<=13; decoder_state<=S13; count<=0; end 13: if(count<SEC7) begin step<=13; decoder_state<=S13; count<=count+1'b1; end else begin step<=14; decoder_state<=S14; count<=0; end 14: if(count<SEC13) begin step<=14; decoder_state<=S14; count<=count+1'b1; end else begin step<=15; decoder_state<=S15; count<=0; end 15: if(count<SEC7) begin step<=15; decoder_state<=S15; count<=count+1'b1; end else begin step<=16; decoder_state<=S16; count<=0; end 16: if(count<SEC7) begin step<=16; decoder_state<=S16; count<=count+1'b1; end else begin step<=17; decoder_state<=S17; count<=0; end 17: if(count<SEC7) begin step<=17; decoder_state<=S17; count<=count+1'b1; end else begin step<=18; decoder_state<=S18; count<=0; end 18: if(count<SEC7) begin step<=18; decoder_state<=S18; count<=count+1'b1; end else begin step<=19; decoder_state<=S19; count<=0; end 19: if(count<SEC7) begin step<=19; decoder_state<=S19; count<=count+1'b1; end else begin step<=20; decoder_state<=S20; count<=0; end 20: if(count<SEC7) begin step<=20; decoder_state<=S20; count<=count+1'b1; end else begin step<=21; decoder_state<=S21; count<=0; end 21: if(count<SEC13) begin step<=21; decoder_state<=S21; count<=count+1'b1; end else begin step<=22; decoder_state<=S22; count<=0; end 22: if(count<SEC7) begin step<=22; decoder_state<=S22; count<=count+1'b1; end else begin step<=23; decoder_state<=S23; count<=0; end 23: if(count<SEC7) begin step<=23; decoder_state<=S23; count<=count+1'b1; end else begin step<=24; decoder_state<=S24; count<=0; end 24: if(count<SEC7) begin step<=24; decoder_state<=S24; count<=count+1'b1; end else begin step<=25; decoder_state<=S25; count<=0; end 25: if(count<SEC7) begin step<=25; decoder_state<=S25; count<=count+1'b1; end else begin step<=26; decoder_state<=S26; count<=0; end 26: if(count<SEC7) begin step<=26; decoder_state<=S26; count<=count+1'b1; end else begin step<=27; decoder_state<=S27; count<=0; end 27: if(count<SEC7) begin step<=27; decoder_state<=S27; count<=count+1'b1; end else begin step<=28; decoder_state<=S28; count<=0; end 28: if(count<SEC13) begin step<=28; decoder_state<=S28; count<=count+1'b1; end else begin decoder_state<=S0; count<=0; end default: decoder_state<=S0; endcase end always@(*) begin case(decoder_state) S0: begin A=RED; end S1: begin A=YELLOW; end S2: begin A=GREEN; end S3: begin A=BLUE; end S4: begin A=COKLAT; end S5: begin A=BLACK; end S6: begin A=PURPLE; end S7: begin A=ORANGE; end S8: begin A=PURPLE; end S9: begin A=BLACK; end S10: begin A=COKLAT; end S11: begin A=BLUE; end S12: begin A=GREEN; end S13: begin A=YELLOW; end S14: begin A=RED; end S15: begin A=YELLOW; end S16: begin A=GREEN; end S17: begin A=BLUE; end S18: begin A=COKLAT; end S19: begin A=BLACK; end S20: begin A=PURPLE; end S21: begin A=ORANGE; end S22: begin A=PURPLE; end S23: begin A=BLACK; end S24: begin A=COKLAT; end S25: begin A=BLUE; end S26: begin A=GREEN; end S27: begin A=YELLOW; end S28: begin A=RED; end default: begin A=RED; end endcase end endmodule
yup..and i want the coding of that..
...............................................................................exmple : if i want 3 bit (001) which i assume to be 1.2 will be 1 as output....???plz help me with this coding....??
//below is the coding that i have done..the above description is the question i ask for upgrading the coding below..can u help me?
based on above statements max value is 2.4 . so if you take an 8 bit binary ( two bit for integer & 6 bit for fraction)parameter RED =3'b000; //if assume as 0 round off ~ 0
parameter YELLOW =3'b001; //if assume as 1.2 round off ~1
parameter GREEN =3'b010; //if assume as 2.1 round off ~ 2
parameter BLUE =3'b011; //if assume as 1.7 round off ~ 2
parameter COKLAT =3'b100; //if assume as 0.2 round off ~ 0
parameter BLACK =3'b101; //if assume as 1.4 round off ~ 1
parameter PURPLE =3'b110; //if assume as 2.4 round off ~ 2
parameter ORANGE =3'b111; //if assume as 0.8 round off ~ 1
parameter BLUE =3'b011; //if assume as 1.7 round off ~ 2
000 - 0.0
001 - 0.5
010 - 1.0
011 - 1.5
100 - 2.0
101 - 2.5
110 - 3.0
111 - 3.5
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 reg [1:0] round_off; case (color) RED : round_off <= 0; YELLOW : round_off <= 1; GREEN : round_off <= 2; BLUE : round_off <= 2; COKLAT : round_off <= 0; BLACK : round_off <= 1; PURPLE : round_off <= 2; ORANGE : round_off <= 1; endcase
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