If your looking for a quick pulse (say to clear a reg/combinatorial) then your coding the problem incorrectly.. never use gate delays.. there is always ways around it.. just hard to figure out..
I think it's no way to create a pulse in degital ckt,
(use a faster clock is not a pulse)
I think you need a hard-macro
(Delay cell, use spice to calculate the delay to meet your pulse width)
then in verilog:
wire pulse,pulsed,pulse_want;
dly(.out(pulsed), .in(pulse));
assign pulse_want = pulse& ~pulsed;
Your problem is not very clear. If you are having a clock signal and an enable signal which when arrives you must give out exactly one pulse, then, you can use two flips flops clocked by the same clock.
O/p of the first flip flop goes as input to the second and the output of the second goes as I/p clear to the first, take o/p from the o/p of the first flip flop, this will be a single cycle pulse.
Your enable can be any cycle width. Nest pulse will be generated only when enable comes for the second time. Tell me if it is clear ???
If your looking for a quick pulse (say to clear a reg/combinatorial) then your coding the problem incorrectly.. never use gate delays.. there is always ways around it.. just hard to figure out..