How to write a peripheral (using Verilog) in Xilinx EDK 6.3 peripheral mode

[vivek]

Hi
does anyone know how to write a peripheral in verilog in xilinx EDK 6.3 peripheral mode???

i was trying to write a peripheral in verilog for the PLB bus in virtex II pro. but after using the peripheral creation wizard it gave a template in VHDL. it is given in documentation that verilog periherals are not supported???!!!! 8O 8O

How can i write a peripheral in verilog then. Has anyone encountered this problem.. please help..