Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
can you tell me what is the memory bist module?
you mean it is memory module which used in verfiacation envirnment (simulation )
if you want to write a simulative-module --
please use a Verilog OR vhdl --but you must grip the behavior of your memory
usually, bist_insertion is done by script(perl,..) on the netlist.
you need to write 2 scripts to do the following things on your netlist:
1. bist_wrapper insert:
search RAM in netlist
2. bist_wrapper join
join alll bist_wrapper and connect them to you bist_controller.
Your can search Internet fow bist doc, and write script yourself.
If you want to write the actual BIST logic from scratch (i.e. not use someone elses code), the you need to web search for the "March G" algorithm. Look for a paper by AJ van de Goor. Most March tests are for bit oriented memory, so also look for his paper about word-orientated March tests.