How to write a delay program in VHDL?

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delay

I am new in VHDL, can anyone give me suggestion how to write a delay program? I just can use "if else", "case" command.
thanks a lot~

in fact, i want to write a loop filter program, i start from writing delay program, am i right?
thx~
 

Re: delay

Hi..
a sequential delay can be achieved using a Delay FF.
Here is an example for an Asynchronous Delay flipflop using Vhdl.

library IEEE;
use IEEE.std_logic_1164.all;

entity delaytest is
port (
clk,rst : in std_logic;
Din : in std_logic;
Dout : out std_logic);
end delaytest;

architecture delaytest of delaytest is
begin

Process(clk,rst)
begin
if rst = '1' then
Dout<= '0';
elsif clk'event and clk = '1' then
Dout<= Din;
end process;

end Delaytest;
 

Re: delay

thanks for your reply!

then how about i use "shift" command? can it be use instead of delay program?
does it work in the loop filter program?

really thx a lot~
 

delay

Operator: sla

Shift left arithmetic operator.
Example: Addr <= Addr sla 8;
Operator: sll
Shift left logical operator.
Example: Addr <= Addr sll 8;

Operator: sra
Shift right arithmetic operator.
Example: Addr <= Addr sra 8;

Operator: srl
Shift right logical operator.
Example: Addr <= Addr srl 8;


These are the shift commands in VHDl. If you uses simply these commands you wont get a delay logic.. since this is only combinational shift. delay can implemented bylatching the shifted values to a register
 

Re: delay

I think I get what you mean.
But i don't know how to write a loop filter...
Is it a simple way for me to write a delay program first?
I am not sure what i need to start at.
 

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