How to write a DAC in VHDL code?

[kun]

can anyone tell me how to write a simple
DAC VHDL

i know help on that please~~~

friday got to hand in

meanwhile i tryiing myself too

if this is in Verilog Module
how to cover to VHDL
anyone please ~~

module dac(DACout, DACin, Clk, Reset);
output DACout;
reg DACout;
input Clk;
input Reset;

reg ['MSBI+2:0] DeltaAdder;
reg ['MSBI+2:0] SigmaAdder;
reg ['MSBI+2:0] SigmaLatch;
reg ['MSBI+2:0] DeltaB;

always @(SigmaLatch) DeltaB - {SigmaLatch['MSBI+2], SIgmaLatch['MSBI+2]} << ('MSBI+1);

always @(DACin or DelataB) DeltaAdder = DACin + DeltaB;

always @(DelaAdder or SigmaLatch) SigmalAdder = DeltaAdder + SigmaLaych;

always @(posedge Clk or posedge Reset)

begin
IF(Reset)
begin
SigmaLatch <= #1 1'b1 << ('MSBI+1);
DACout <= #1 1'b0;
end
else
begin
SigmaLatch <== #1 SigmaAdder;
DACout <= #1 SigmaLatch['MSBI+2];
end
end
endmodule

 

[echo47]

How to write a DAC

I don't know how to convert Verilog to VHDL, but the code you've shown won't work due to typographical errors.
The original module is in Xilinx application note 154, "Virtex Synthesizable Delta-Sigma DAC":
https://www.xilinx.com/bvdocs/appnotes/xapp154.pdf

Maybe someone else can help you convert it to VHDL.