Sep 26, 2017 #1 S sanjaysharmaiitk Member level 1 Joined Jul 28, 2017 Messages 33 Helped 0 Reputation 0 Reaction score 0 Trophy points 6 Location KANPUR Activity points 280 how to write testbench for "INPUT" pin in verilog i have designed a verilog code for uart for that i need to use bidirectional data buses for that inout pin is used in verilog code but in test bench i dont know how to assign data to inout port and read data from inout port. Last edited: Sep 26, 2017
how to write testbench for "INPUT" pin in verilog i have designed a verilog code for uart for that i need to use bidirectional data buses for that inout pin is used in verilog code but in test bench i dont know how to assign data to inout port and read data from inout port.
Sep 26, 2017 #2 dpaul Advanced Member level 5 Joined Jan 16, 2008 Messages 1,799 Helped 317 Reputation 635 Reaction score 342 Trophy points 1,373 Location Germany Activity points 13,074 Have you searched for your answer? I don't think so.....so many links out there explaining how to drive inout ports via TB. One of them - https://stackoverflow.com/questions/31391112/bidirectional-port-in-verilog-testbench
Have you searched for your answer? I don't think so.....so many links out there explaining how to drive inout ports via TB. One of them - https://stackoverflow.com/questions/31391112/bidirectional-port-in-verilog-testbench