how to wire testbench for "INPUT" pin in verilg

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sanjaysharmaiitk

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how to write testbench for "INPUT" pin in verilog

i have designed a verilog code for uart for that i need to use bidirectional data buses for that inout pin is used in verilog code but in test bench i dont know how to assign data to inout port and read data from inout port.
 
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