corgan
Member level 3
pdm decimation filter
I design a decimation filter(in verilog) for a 1-bit oversampled sigma-delta ADC.
But I don't have any idea to verify it.
Could anyone give me a hand?
Thanks a lot!
I design a decimation filter(in verilog) for a 1-bit oversampled sigma-delta ADC.
But I don't have any idea to verify it.
Could anyone give me a hand?
Thanks a lot!