Its very simple to use Xilinx coregen FIFOs. Just make sure that you have applied proper clock to the FIFO and it should be up all the time. Then follow the steps below:
1. Make sure data to be written is available and stable.
2. Put it on "din" signal. Don't assert "wr_en" at the same clock edge when you put data on "din".
3. After a while, assert "wr_en" for a single clock cycle. Before executing this step, dont change the data. It may cause you to put wrong(garbage) data into the FIFO.
4. After a while, update data on "din" or goto step 2.
Complete your state machine buddy! I am not sure what are you trying to implement? Following state descriptions may help you:
1. IDLE state: wait in this state until you get the new data, after having data goto 2.
2. Start WRITE state: Assert wr_en, goto 3.
3. Stop WRITE State: Deassert wr_en, goto 1.