Bare in mind, that the simulation capabilities of Quartus / ISE are limited.
Generaly, the use of synthesis tools for simulation is discouraged. I suggest you work with a designated simulator (such as ModelSim or Active HDL) while being assisted by the synthesizers RTL viewer to get the idea of how your code is translated into logic.
I don't discourage the use of ISim - What I said is that the use of FPGA vendor tools for simulation is being generally discouraged.
I'm sure that ISim and Quartus have there place - maybe for simpler designs.
Altera itself advocates the use of ModelSim even though it spent good time and money designing its own simulator.
I've heard that ISim doesn't have full support for VHDL 2008 and No system verilog support.
Altera have stopped developing their simulator. It is not available from Q9+
Xilinx are working to make their simulator work better (but it doesnt work as well as modelsim. It has poor support on some of the lesser used parts of VHDL eg protected types - But I keep finding bugs for those in modelsim too and 2008 support doesnt exist yet)
Generally speaking, Quartus and ISE are decent synthesis tools...but sim wise - they're considered inferior to the big players from Mentor and Synopsys.
I hope Altera and Xilinx focus their resources on making better PLDs instead of competing on that extra buck from selling CAD software.
Take a look at Actel - being a much smaller company then Xilinx and Altera, they make very few software tools. Yet, they have a very interesting product portfolio...
For altera, you cant get better than Quartus for Synthesis for altera - Synopsis will admit as much. Altera do a lot of work on their tools and they are pretty good. Afaik, there are no synthesis tools that fully support VHDL 2008 yet (altera support a few handy bits, afaik Xilinx dont support any). Xilinx have always focussed more on products rather than their tools, hence why their own tools have always had a pretty poor reputation, while altera have always worked hard and not really allowed other companies to write synthesis software. Synopsys are just started to support VHDL 2008.
MrFlibble. Ive never given Verilog a go. But Everything I read makes me think Ill just get pissed off with vanila Verilog. But I hear SystemVerilog is where it's at in terms of Verification. But VHDL has done fine for me so far (bitmap reading/writing, random stimulus generation, behavioural models - one of which included a lot of linked lists!).
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